1. Field of the Invention
The present invention relates generally to semiconductor devices, and, more particularly, to an improvement of a structure of a peripheral region of a bonding pad by which cracks and leaks in a semiconductor device, particularly as may be generated in a bonding step, can be prevented.
2. Background of the Prior Art
FIG. 11 is a diagram of a layout of a random access memory chip shown as an example of a semiconductor device. A semiconductor memory device 1 has an integrated circuit such as a memory cell array 2 in its central region, and has a plurality of bonding pads 3 located in its peripheral region. The bonding pads 3 are electrode portions for lead connection for leading a signal from the inside of an element to the outside thereof. FIG. 12 shows a sectional structure of the peripheral portion including the bonding pad 3 taken along a cut line A in the semiconductor chip 1. FIG. 12 is a sectional view schematically showing a structure of a semiconductor integrated circuit. MOS transistors 5, 5 constituting an integrated circuit are formed on a major surface of a semiconductor substrate 4. The MOS transistors 5, 5 are insulated and isolated with a field oxide film 30 for element isolation provided therebetween. The major surface of the semiconductor substrate 4 is covered with a thick interlayer insulating film 7. In addition, a bonding pad 3 is formed at a predetermined position on the surface of the interlayer insulating film 7. Furthermore, a passivation film 8 is formed on the surface of the interlayer insulating film 7 on which the bonding pad 3 is formed. The passivation film 8 has an opening portion on the surface of the bonding pad 3. A wire 9 for connecting an external lead is welded on the surface of the exposed bonding pad 3.
A description will now be given of the bonding of a bonding pad and an external lead in the semiconductor chip 1. The bonding pad 3 is formed of aluminum (Al) or the like and the wire 9 is also formed of Al, Au or the like. There are various methods of wire bonding and, in general, a thermal and pressurized connection scheme or a supersonic scheme are often used. The wire bonding of the thermal and pressurized connection scheme is a method of connecting the bonding pad 3 and the wire 9 by applying heat and pressure. The supersonic wave scheme is a method of rubbing contact surfaces of the bonding pad 3 and the wire 9 to mechanically connect both the metals by pressing the wire 9 on the surface of the bonding pad 3 to vibrate the same. Accordingly, in these bonding methods, especially in the later method, both mechanical impact and pressure affect the surface of the bonding pad 3. The impact is propagated through the interlayer insulating film 7 under the bonding pad 3 to reach the field oxide film 30 or which further applies the impact on the surface of the semiconductor substrate 4 directly under the field oxide film 30. This deteriorates a crystalline structure of a surface region of the semiconductor substrate 4. In case the impact is stronger, a crack may be formed in the interlayer insulating film 7. Deterioration of the surface of the semiconductor substrate 4 and the formation of a crack 11 in the bonding step, as described, can cause such trouble as follows in a function test later:
a. An invention layer is formed between two MOS transistors 5, 5 isolated with the field oxide film 30 located directly under the bonding pad 3 provided therebetween to generate a conducting current 10.
b. A leak is generated between the bonding pad 3 and the semiconductor substrate 4 along the crack 11 formed from the bonding pad 3 toward the semiconductor substrate 4.
Since there is no means for restoring such a semiconductor chip, the chip is discard as defective. Therefore, yield in the manufacture of such semiconductor devices is reduced, resulting in a decrease of productivity.
On the other hand, there is another method of preventing the formation of crack or the like by reducing the pressure of the wire 9 onto the bonding pad 3 in the bonding step. However, this method is found to be difficult for the following reasons. FIG. 13 is a diagram showing a correlation between the pressure applied on the bonding pad and the adhesive strength of the wire, and the crack generation rate. First, in order to obtain reliability of adhesiveness between the bonding pad 3 and the wire 9, it is necessary to ensure constant adhesive strength F.sub.WL. Namely, the pressure F onto the bonding pad is required to be F.sub.1 or more. However, the crack generation rate C is increased approximately in proportion with the pressure F. Accordingly, in order to hold the crack generation rate below the allowable value C.sub.L, the pressure F is required to be F.sub.2 or below. Considering both the requirements of the pressure F, an applicable pressure F is limited in the range of F.sub.1 &lt;F&lt;F.sub.2 in the drawing. However, the range is limited to be very narrow in many cases because of a stacked layer structure, a material structure of the bonding pad 3 or the like of the device in practical use. In addition, a margin for the pressure should be counted. Accordingly, a method of suppressing the formation of crack and the like by adjusting the pressure onto the bonding pad in bonding is not perfectly effective means in practice.